1. Field of the Invention
This invention generally relates to isolation circuitry and, more particularly, to a multistage cell that eliminates uncertainty when reestablishing signal flow between isolated modules.
2. Description of the Related Art
Combinational logic devices are designed to obey AND, OR, NOR NAND, NOT, or XOR logic tables. The output of combinational logic isolation cells have no “memory” of any previous input or output values. As seen in the tables below, it is possible to hold a combinational logic output value to a known state by controlling the input values.
Table A is an OR type logic table.
TABLE AISO ADQ000011101111
Table B is an AND type logic table.
TABLE BISO ADQ000010100111
FIG. 9 is a schematic diagram of system using combinational logic isolation cells, presented to illustrate a problem that may occur when one of the modules in the system is powered down (prior art).
FIG. 10 is a timing diagram associated with the system of FIG. 9. Here, every time ISO A signal is set (indicating Block A is in Power Down), OR isolation cell 900 sets the “DATA VALID” signal to Block B and hence Block B starts sampling invalid data when Block A is actually in power down.
In contrast, a latch is a device with two possible stable states, making it possible to store a bit of information in “memory”. The memory is typically created using one of the above-mentioned combinational logic functions in a feedback configuration. SR latches and JK latches are well known in the art. A gated latch (e.g., a gated SR latch) may incorporate a reset function. A slightly more complicated example of a latch is a flip-flop.
Table C is an exemplary latch logic table.
TABLE CISO ADQ[n + 1]1001110XQ[n]
FIG. 1 is a schematic block diagram illustrating a system using a single stage latch as an isolation cell (prior art).
FIG. 2 is a timing diagram associated with the staggered power up of the system of FIG. 1 (prior art). Considering both FIGS. 1 and 2, a latch 100 may generate an unexpected transition at the output Q as shown in FIG. 2 (Case 2: Q). The uncertainty is because the value of the feedback loop in the latch can't be predicted the first time the ISO A enable port is triggered. That is, the latch input value from the previous enable cycle is unknown. Initially, Block B 102 is powered up (PWR DOWN B goes low), followed by a reset (RESET B). Then, Block A 104 is powered up. Before Block A is reset, the ISO A signal triggers the latch isolation cell 100 to operate so that any signal appearing on the D port input is transferred to the Q port output. After ISO A goes low, Block A receives the RESET A signal. After RESET A, Block A outputs a data signal (D). If Block B is only designed to handle Case 1, where the value of Q matches the value of D, then the Block B may malfunction due to the unexpected transition on Q (Case 2). When designing a staggered power up, where modules are switched on one after the other, a manual verification must therefore be performed to ensure that the signal timings as correct in all conditions. This process is very time consuming and prone to errors.
Upon startup, the latch isolation cell could supply either a “1” or “0” value, and verification is required to determine if Block B 102 can tolerate the uncertainty. If Block 104 had n outputs, with n corresponding latch isolation cells, there would be 2n combinations against which Block 102 would need tolerance verification. For example, Block A may have 8 outputs isolated using 8 latch isolation cells (there rarely ever is just one signal going from Block A to Block B). Since the 8 latch isolation cells output either 1 or 0, there are 28=256 combinations of outputs. Verification must be performed to determine if Block 102 can accept all of the possible combinations without going into a bad state.
It would be advantageous if electronic modules could be isolated with a latch circuit having predictable outputs.